1. Field of the Invention
This invention relates to processors and more specifically to dynamically controlling processor voltage and frequency.
2. Description of the Related Art
Integrated circuits such as microprocessors can be run at different clock speeds and with different supply voltages. The selection of the appropriate clock speed and appropriate voltage depends on many factors. A higher clock speed requires a higher supply voltage. In addition, the higher clock speed results in additional heat and power being dissipated. Microprocessors utilized in mobile applications, i.e., those used in battery powered systems, are particularly sensitive to power considerations and therefore generally require the lowest supply voltage that can achieve the rated clock speed. That is in part due to the small, densely packed system construction that limits the ability of the computer system to safely dissipate the heat generated by computer operation.
Many power saving techniques have been introduced to try and mitigate the limitations caused by thermal and battery power constraints. The frequency of operation (clock frequency) of the processor and its operating voltage determines its power consumption. Since power consumption and therefore heat generation are roughly proportional to the processor""s frequency of operation, scaling down the processor""s frequency has been a common method of staying within appropriate power limitations.
A common power management technique called xe2x80x9cthrottlingxe2x80x9d prevents the processor from over heating by temporarily placing the processor in a stop grant state. During the stop grant state the processor does not execute operating system or application code and typically has its clocks gated internally to reduce power consumption. Throttling is an industry standard method of reducing the effective frequency of processor operation and correspondingly reducing processor power consumption by using a clock control signal (e.g. the processor""s STPCLK# input) to modulate the duty cycle of processor operation. A temperature sensor monitors the processor temperature to determine when throttling is needed. Throttling continuously stops and starts processor operation and reduces the effective speed of the processor resulting in reduced power dissipation and thus lowering processor temperature.
Referring to FIG. 1, one prior art system capable of implementing throttling is illustrated. Processor (CPU) 101 receives voltage 102 from voltage regulator 103. The voltage regulator is controlled by voltage identification (VID) signals 104 which are set by system jumper settings 105. A clock multiplier value 107, supplied from system jumper settings 105 (bus frequency (BF)[2:0]) is supplied to CPU 101. CPU 101 multiplies a received bus clock 109 by the multiplier value 107 to generate the core clocks for the processor.
CPU 101 receives a STPCLK# (the # sign indicates the signal is active low) input, which is used to temporarily suspend core clock operation and conserve power. An asserted STPCLK# signal results in the processor entering a stop grant state. In that state, execution of operating system (OS) and application code is stopped, and the core clocks are typically stopped although some minimum logic including clock multiplier logic may still operate.
While throttling is effective to reduce power consumption, it would be desirable to dynamically adjust the operating frequency and voltage of the processor to match operating conditions. For example, microprocessors, particularly those used in battery powered systems, sometimes operate in environments where external power is available, e.g., from an AC adapter or in docking stations. In such circumstances, it would be desirable to operate the processor with increased performance. That is, to provide higher supply voltage and higher clock speeds. Therefore, it would be desirable if the computer system could adapt readily to its environment in order to provide the appropriate level of performance given the operating environment. Further, it would be preferable to dynamically adjust to the demands of the various environments without the need for chipset or other external support. It is also desirable to adjust processor voltage and frequency based on CPU utilization by the applications which are running on the processor. That would allow for the processor to save power when its full computing bandwidth is not required.
Accordingly, the invention provides a processor that can enter an internally generated stop grant state in which the processor does not execute operating system or application code and during which, processor operating voltage and frequency can be changed. The stop grant state can be entered by accessing a predetermined register on the processor. The invention further provides the ability to write to registers on the processor to specify new voltage and frequency control values to dynamically provide operating voltage and frequencies that correspond to the current operating environment. The new voltage and frequency control values are applied to appropriate control logic during the internally generated stop grant state. An internal count circuit is utilized to determine the duration of the internally generated stop grant state. That count circuit may also be programmable to adjust the duration of the internally generated stop grant state.
According to an embodiment of the present invention, changes to core clock frequency and core voltage are made by writing to software programmable locations on the processor to store voltage ID (VID) values to specify core voltage and clock frequency control values, which are supplied to the clock generation logic to specify core clock frequency. The processor enters an internal stop grant state in which the processor does not execute operating system or application code. After entering the stop grant state, the processor core voltage and core frequency may be adjusted. A timing mechanism on the processor allows the new voltage and clock frequency to stabilize before exiting the stop grant state and resuming code execution. The timing mechanism may include a programmable count to specify the time to allow the new voltage and clock frequency to stabilize.
In another embodiment, the invention provides a method for changing frequency of a core clock being supplied to a core logic region of an integrated circuit. The method includes accessing a control register in the integrated circuit. In response to accessing the control register, execution of operating system and application code in the core logic region is stopped and the processor enters a stop grant state. Once in the stop grant state, new clock control values may be applied to clock generation logic on the processor. After an interval determined according to a count circuit in the integrated circuit, the stop grant state is exited and the processor resumes execution of operating system and application code. The method further includes writing a new voltage control value to a software programmable voltage control register in the processor and applying the new voltage control value during the internally generated stop grant state.